Border scan, also known as JTAG, is a standard method for testing all interconnections on printed circuit boards (PCBs) using boundary scan cells. It was developed by the Joint Test Action Group (JTAG) in the 1980s and standardized as IEEE Std. 1149.1-1990. Border scans are used throughout the entire product lifecycle and offer advantages such as lower equipment costs, short test times, better test coverage, and higher product quality.
A border scan is a method of testing all interconnections on printed circuit boards (PCBs) using border scan cells instead of physical probes. It is a standard widely adopted by electronic companies. Prototype debugging and product design can also benefit from boundary scans.
In the early 1980s, PCB manufacturers relied on in-circuit testers and physical bed-of-nails devices to test components. With the advent of increasingly miniaturized components, higher device density, multilayer boards, and surface mount packaging, it has become increasingly difficult to physically access all the interconnects on a PCB. In-circuit testing is essential for examining manufacturing defects such as open and short circuits and damaged or missing components. It became necessary to develop a different methodology for testing PCBs without requiring physical access to all components on the board.
The solution, developed by the Joint Test Action Group (JTAG), was to create physical access to all components within the device itself. This group of engineers created the process for boundary scan testing in the 1980s. In 1990, it was standardized as IEEE Std. 1149.1-1990.
While JTAG did not invent the concept itself, it was instrumental in converting the basic idea into an international standard. Currently, a border scan is also known as JTAG. A revision of the IEEE standard. 1149.1 was introduced in 1993 and this was called 1149.1a. This particular revision consisted of a few improvements and clarifications. Later, a supplement describing the Boundary-Scan Description Language (BSDL) was added in 1994.
Physical access was built into the device by including serial shift registers internal to its boundaries. These logs are called boundary scan logs and can be thought of as virtual nails. They can be used to test all interconnects on the PCB. Boundary scan logs are found at the beginning and end of areas most likely to be damaged during board assembly. This is also called the interconnect region.
These boundary scan registers or cells can force and acquire data from a device’s pins. The data obtained in this way is compared with the expected results to test board failures. This is a much easier way to test components for proper fit, work function, and alignment. Border scans were initially used in the manufacturing phase of a product’s lifecycle, but due to the establishment of the IEEE-1149.1 standard, they are currently used throughout the entire product lifecycle.
The advantage of using border scans to test PCBs is lower equipment costs, which speeds up development; short test times; better test coverage; and higher product quality. Electronics manufacturers around the world rely on border scans to test PCBs effectively and cost-effectively.
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